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ltc4269-2 1 42692fb typical application features applications description ieee 802.3at high power pd and synchronous forward controller with aux support the ltc ? 4269-2 is an integrated powered device (pd) interface and power supply controller featuring 2-event classiication signaling, lexible auxiliary power op- tions, and a power supply controller suitable for syn- chronously rectiied forward supplies. these features make the ltc4269-2 ideally suited for an ieee802.3at pd application. the pd controller features a 100v mosfet that isolates the power supply during detection and classiication, and provides 100ma inrush current limit. also included are power good outputs, an undervoltage/overvoltage lock- out and thermal protection. the current mode forward controller allows for synchronous rectiication, resulting in an extremely high eficiency, green product. soft-start for controlled output voltage start-up and fault recovery is included. programmable frequency over 100khz to 500 khz allows lexibility in eficiency vs size and low emi. n 25.5w ieee 802.3at compliant (type-2) pd n poe + 2-event classiication n ieee 802.3at high power available indicator n integrated state-of-the-art synchronous forward controller C isolated power supply eficiency >94% n flexible auxiliary power interface n superior emi performance n robust 100v 0.7 (typ) integrated hot swap? mosfet n integrated signature resistor, programmable class current, uvlo, ovlo and thermal protection n short-circuit protection with auto-restart n programmable switching frequency from 100khz to 500khz n thermally enhanced 7mm 4mm dfn package n ip phones with large color screens n dual radio 802.11n access points n ptz security cameras + t2p v neg v portn shdn r class v portp pgnd to micro- controller gnd blank delay 82k 30.9 332k 158k 133 10k 5.1 158k 22.1k 33k 1.5k 50m 2k 1.2k tlv431 v cc 11.3k 3.65k 42692 ta01 22k 0.22f 0.1f r osc v ref fb comp i sense oc ss_maxdc sd_v sec v in pwrgd s out ltc4269-2 0.1f 10f v cc 33k 237k 2.2f + 10f 10h 1mh 6.8h 10.0k out 4.7nf 0.1f 54v from data pair 54v from spare pair +C ~~ +C ~~ 4.7nf 10nf + 220f 5v5a poe-based self-driven synchronous forward power supply l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and hot swap, thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. downloaded from: http:///
ltc4269-2 2 42692fb pin configuration absolute maximum ratings (notes 1, 2) top view 33 dkd package 32-lead (7mm s 4mm) plastic dfn shdn 1 t2p 2 r class 3 nc 4 v portn 5 v portn 6 nc 7 nc 8 comp 9 fb 10 r osc 11 sync 12 ss_maxdc 13 v ref 14 sd_v sec 15 gnd 16 32 v portp 31 nc 30 nc 29 pwrgd 28 pwrgd 27 v neg 26 v neg 25 nc24 sout 23 v in 22 out21 pgnd 20 delay 19 oc 18 i sense 17 blank t jmax = 125c, ja = 34c/w, jc = 2c/w exposed pad (pin 33) must be soldered to heat sinking plane that is connected to gnd order information lead free finish tape and reel part marking* package description temperature range ltc4269cdkd-2#pbf ltc4269cdkd-2#trpbf 42692 32-lead (7mm 4mm) plastic dfn 0c to 70c ltc4269idkd-2#pbf ltc4269idkd-2#trpbf 42692 32-lead (7mm 4mm) plastic dfn C40c to 85c lead based finish tape and reel part marking* package description temperature range ltc4269cdkd-2 ltc4269cdkd-2#tr 42692 32-lead (7mm 4mm) plastic dfn 0c to 70c ltc4269idkd-2 ltc4269idkd-2#tr 42692 32-lead (7mm 4mm) plastic dfn C40c to 85c consult ltc marketing for parts speci ied with wider operating temperature ranges. *the temperature grade is identiied by a label on the sh ipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speciications, go to: http://www.linear.com/tapeandreel/ pins with respect to v portn v portp voltage ........................................ C0.3v to 100v v neg voltage ......................................... C0.3v to v portp v neg pull-up current ..................................................1a shdn ....................................................... C0.3v to 100v r class , voltage ........................................... C0.3v to 7v r class source current ..........................................50ma pwrgd voltage (note 3) lo w impedance source .... v neg C 0.3v to v neg + 11v sink current .........................................................5ma pwrgd , t2p voltage ............................... C0.3v to 100v pwrgd , t2p sink current .....................................10ma pins with respect to gnd v in (note 4) ................................................ C0.3v to 25v sync, ss_maxdc, sd_v sec , i sense , oc .................................................... C0.3v to 6v comp, blank, delay .............................. C0.3v to 3.5v fb ................................................................ C0.3v to 3v r osc current ........................................................ C50a v ref source current ..............................................10ma operating ambient temperature range lt c4269c-2 ............................................. 0c to 70c lt c4269i-2 ..........................................C40c to 85c downloaded from: http:///
ltc4269-2 3 42692fb electrical characteristics the l denotes the speciications which apply over the full operating temperature range, otherwise speciications are at t a = 25c. parameter conditions min typ max units interface controller (note 5) operating input voltage signature range classiication range on voltage undervoltage lockout overvoltage lockout at v portp (note 6) l l l l 1.5 12.5 30.0 71.0 60 9.8 21.0 37.2 v v v v v v on/uvlo hysteresis window l 4.1 v signature/class hysteresis window l 1.4 v reset threshold state machine reset for 2-event classiication l 2.57 5.40 v supply current supply current at 57v measured at v portp pin l 1.35 ma class o current v portp = 17.5v, no r class resistor l 0.40 ma signature signature resistance 1.5v v portp 9.8v (note 7) l 23.25 26.00 k invalid signature resistance, shdn invoked 1.5v v portp 9.8v, v shdn = 3v (note 7) l 11 k invalid signature resistance during mark event (notes 7, 8) l 11 k classiication class accuracy 10ma < i class < 40ma, 12.5v < v portp < 21v (notes 9, 10) l 3.5 % classiication stability time v portp pin step to 17.5v, r class = 30.9, i class within 3.5% of ideal value (notes 9, 10) l 1 ms normal operation inrush current v portp = 54v, v neg = 3v l 60 100 180 ma power fet on-resistance tested at 600ma into v neg , v portp = 54v l 0.7 1.0 power fet leakage current at v neg v portp = shdn = v neg = 57v l 1 a digital interface shdn input high level voltage l 3 v shdn input low level voltage l 0.45 v shdn input resistance v portp = 9.8v, shdn = 9.65v l 100 k pwrgd , t2p output low voltage tested at 1ma, v portp = 57v, for t2p , must complete 2-event classiication to see active low l 0.15 v pwrgd , t2p leakage current pin voltage pulled 57v, v portp = v portn = 0v l 1 a pwrgdp output low voltage tested at 0.5ma, v portp = 52v, v neg = 4v, output voltage is with respect to v neg l 0.4 v pwrgdp clamp voltage tested at 2ma, v neg = 0v, voltage is with respect to v neg l 12.0 16.5 v pwrgdp leakage current v pwrgd = 11v, v neg = 0v, voltage is with respect to v neg l 1 a pwm controller (note 11) operational input voltage i vref = 0a l v in(off) 25 v v in quiescent current i vref = 0a, i sense = oc = open 5.2 6.5 ma v in start-up current fb = 0v, ss_maxdc = 0v (notes 12, 13) l 460 700 a v in shutdown current sd_v sec = 0v (notes 12, 13) l 240 350 a sd_v sec threshold 10v < sd < 25v 1.261 1.32 1.379 v downloaded from: http:///
ltc4269-2 4 42692fb electrical characteristics the l denotes the speciications which apply over the full operating temperature range, otherwise speciications are at t a = 25c. parameter conditions min typ max units sd_v sec(on) current sd_v sec = sd_v sec threshold +100mv 0 a sd_v sec(off) current sd_v sec = sd_v sec threshold C 100mv 8.3 10 11.7 a v in(on) l 14.25 15.75 v v in(off) l 8.75 9.25 v v in(hyst) l 3.75 5.5 7.0 v v ref output voltage i vref = 0 l 2.425 2.5 2.575 v line regulation i vref = 0, 10v < v in < 25v 1 10 mv load regulation 0ma < i vref < 2.5ma 1 10 mv oscillator frequency, f osc r osc = 178k, fb = 1v, ss_maxdc = 1.84v l 165 200 240 khz f osc(min) r osc = 365k, fb = 1v 80 100 120 khz f osc(max) r osc = 64.9k, comp = 2.5v, sd_v sec = 2.64v 440 500 560 khz sync input resistance 18 k sync switching threshold fb = 1v 1.5 2.2 v sync frequency/f osc fb = 1v (note 14) 1.25 1.5 f osc line regulation r osc = 178k; 10v < v in < 25v, ss_maxdc = 1.84v 0.05 0.33 %/v v rosc r osc pin voltage 1 v error ampliier fb reference voltage 10v < v in < 25v, v ol + 0.2v < comp < v oh C 0.2 l 1.201 1.226 1.250 v fb input bias current fb = fb reference voltage -75 -200 na open-loop voltage gain v ol + 0.2v < comp < v oh C 0.2 65 85 db unity-gain bandwidth (note 15) 3 mhz comp source current fb = 1v, comp = 1.6v C4 C9 ma comp sink current comp = 1.6v 4 10 ma comp current (disabled) fb = v ref , comp = 1.6v 18 23 28 a comp high level v oh fb = 1v, i comp = C250a 2.7 3.2 v comp active threshold fb = 1v, sout duty cycle > 0% 0.7 0.8 v comp low level v ol i comp = 250a 0.15 0.4 v current sensei sense maximum threshold comp = 2.5v, fb =1v 197 220 243 mv i sense input current (duty cycle = 0%) comp = 2.5v, fb = 1v (note 12) C8 a i sense input current (duty cycle = 80%) comp = 2.5v, fb = 1v (note 12) C35 a oc threshold comp = 2.5v, fb = 1v 98 107 116 mv oc input current (oc = 100mv) C50 C100 na default blanking time comp = 2.5v, fb = 1v, r blank = 40k (note 16) 180 ns adjustable blanking time comp = 2.5v, fb = 1v, r blank = 120k 540 ns v blank 1 v sout driver sout clamp voltage i gate = 0a, comp = 2.5v, fb = 1v 10.54 12 13.5 v sout low level i gate = 25ma 0.5 0.75 v downloaded from: http:///
ltc4269-2 5 42692fb electrical characteristics the l denotes the speciications which apply over the full operating temperature range, otherwise speciications are at t a = 25c. parameter conditions min typ max units sout high level i gate = C25ma, v in = 12v comp = 2.5v, fb = 1v 10 v sout active pull-off in shutdown v in = 5v, sd_v sec = 0v, sout = 1v 1 ma sout to out (rise) delay (t delay ) comp = 2.5v, fb = 1v (note 16) r delay = 120k 40 120 ns ns v delay 0.9 v out driver out rise time fb = 1v, c l = 1nf (notes 15, 16) 50 ns out fall time fb = 1v, c l = 1nf (notes 15, 16) 30 ns out clamp voltage i gate = 0a, comp = 2.5v, fb = 1v 11.5 13 14.5 v out low level i gate = 20ma i gate = 200ma 0.45 1.25 0.75 1.8 v v out high level i gate = C20ma, v in = 12v comp = 2.5v, fb = 1v i gate = C200ma, v in = 12v comp = 2.5v, fb = 1v 9.9 9.75 v v out active pull-off in shutdown v in = 5v, sd_v sec = 0v, out = 1v 20 ma out max duty cycle comp = 2.5v, fb = 1v, r delay = 10k (f osc = 200khz), v in = 10v, sd_v sec = 1.4v, ss_maxdc = v ref 83 90 % out max duty cycle clamp comp = 2.5v, fb = 1v, r delay = 10k (f osc = 200khz), v in = 10v sd_v sec = 1.32v, ss_maxdc = 1.84v sd_v sec = 2.64v, ss_maxdc = 1.84v 63.5 25 72 33 80.5 41 % % soft-startss_maxdc low level: v ol i ss_maxdc = 150a, oc = 1v 0.2 v ss_maxdc soft-start reset threshold measured on ss_maxdc 0.45 v ss_maxdc active threshold fb + 1v, dc > 0% 0.8 v ss_maxdc input current (soft-start pull-down: i dis ) ss_maxdc = 1v, sd_v sec = 1.4v, oc = 1v 800 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: pins with 100v absolute maximum guaranteed for t 0c, otherwise 90v. note 3: pwrgd voltage clamps at 14v with respect to v neg . note 4: in applications where the v in pin is supplied via an external rc network from a system v in > 25v, an external zener with clamp voltage v in on(max) < v z < 25v should be connected from the v in pin to gnd. note 5: all voltages are with respect to v portn pin unless otherwise noted. note 6: input voltage speciications are deined with respect to ltc4269-2 pins and meet ieee 802.3af/at speciications when the input diode bridge is included. note 7: signature resistance is measured via the ? v/ ? i method with the minimum ? v of 1v. the ltc4269-2 signature resistance accounts for the additional series resistance in the input diode bridge. note 8: an invalid signature after the 1st classiication event is mandated by ieee 802.3at standard. see the applications information section.note 9: class accuracy is respect to the ideal current deined as 1.237/r class and does not include variations in r class resistance. note 10: this parameter is assured by design and wafer level testing. note 11: voltages are with respect to gnd unless otherwise speciied. tested with comp open, v fb = 1.4v, r rosc = 178k, v sync = 0v, v ss(maxdc) set to v ref (but electrically isolated), c vref = 0.1f, v sd_vsec = 2v, r blank = 121k, r delay = 121k, v isense = 0v, v oc = 0v, c out = 1nf, v in = 15v, sout open, unless otherwise speciied. note 12: guaranteed by correlation to static test. note 13: v in start-up current is measured at v in = v in(on) C 0.25v and scaled by 1.18 (to correlate to worst-case v in start-up current at v in(on) . note 14: maximum recommended sync frequency = 500khz. note 15: guaranteed but not tested. note 16: timing for r = 40k derived from measurement with r = 240k. downloaded from: http:///
ltc4269-2 6 42692fb typical performance characteristics input current vs input voltage 25k detection range input current vs input voltage signature resistance vs input voltage class operation vs time on-resistance vs temperature pwrgd, t2p output low voltage vs current fb voltage vs temperature v portp voltage (v) 0 0 v portp current (ma) 0.1 0.2 0.3 0.4 0.5 2 4 6 8 42692 g01 10 t a = 25c v portp voltage rising (v) 0 0 v portp current (ma) 10 20 30 40 50 10 20 30 40 42692 g02 50 60 t a = 25c class 4 class 3 class 2 class 1 class 0 input current vs input voltage v portp voltage (v) 12 9.5 v portp current (ma) 10.5 14 16 42692 g03 10.0 18 20 22 11.0 85c C40c class 1 operation v portp voltage (v) 1 22 v1:v2: signature resistance (k) 23 25 26 27 3 5 42692 g04 24 7 9 6 10 2 4 8 28 resistance = diodes: hd01 t a = 25c = $ v $ i v2 C v1 i 2 C i 1 ieee upper limit ieee lower limit ltc4269-2 + 2 diodes ltc4269-2 only junction temperature (c) C50 0.2 resistance (?) 0.4 0.6 0.8 1.0 1.2 C25 0 25 50 42692 g06 75 100 active high pwrgd output low voltage vs current current (ma) 0 0 pwrgd (v) 0.4 1.0 0.5 1 42692 g08 0.2 0.8 0.6 1.5 2 t a = 25c v portp C v neg = 4v temperature (c) C50 1.20 fb voltage (v) 1.22 1.25 0 50 75 42692 g09 1.21 1.24 1.23 C25 25 100 125 v portp input voltage 10v/div class current 10ma/div time (10s/div) 42692 g05 t a = 25c current (ma) 0 v pwrgd C v portn (v) v t2p C v portn (v) 0.4 0.6 8 42692 g07 0.2 0 2 4 6 10 0.8 t a = 25c downloaded from: http:///
ltc4269-2 7 42692fb typical performance characteristics switching frequency vs temperature v in shutdown current vs temperature v in start-up current vs temperature i q (v in ) vs temperature sd_v sec turn on threshold vs temperature sd_v sec pin current vs temperature v in turn on/off voltage vs temperature comp active threshold vs temperature comp source current vs temperature temperature (c) C50 155 switching frequency (khz) 185 245 0 50 75 42692 g10 170 230215 200 C25 25 100 125 temperature (c) C50 100 v in shutdown current (a) 200 500 0 50 75 42692 g11 150 400300 450350 250 C25 25 100 125 v in = 15v sd_v sec = 0v temperature (c) C50 3.5 i q (ma) 4.5 6.5 0 50 75 42692 g13 4.0 6.05.5 5.0 C25 25 100 125 oc = open temperature (c) C50 1.22 sd_v sec turn on threshold (v) 1.27 1.42 0 50 75 42692 g14 1.37 1.32 C25 25 100 125 temperature (c) C50 0 sd_v sec pin current (a) 15 0 50 75 42692 g15 10 5 C25 25 100 125 0ma pin current afterpart turn on pin current beforepart turn on temperature (c) C50 0 comp (v) 0.4 1.61.4 1.2 0 50 75 42692 g17 0.2 1.00.8 0.6 C25 25 100 125 r isense = 0k temperature (c) C50 5.0 comp source current (ma) 12.5 0 50 75 42692 g18 10.0 7.5 C25 25 100 125 current out of pin fb = 1vcomp = 1.6v temperature (c) C50 v in startup current (a) 200 500 0 50 75 42692 g12 400300 450 600550 350 250 C25 25 100 125 sd_v sec = 1.4v temperature (c) C50 6 8 v in (v) 1816 14 12 0 50 75 42692 g16 10 C25 25 100 125 v in turn off voltage v in turn on voltage downloaded from: http:///
ltc4269-2 8 42692fb typical performance characteristics comp sink current vs temperature (disabled) comp pin current vs temperature i sense maximum threshold vs comp i sense maximum threshold vs temperature i sense pin current (out of pin) vs duty cycle i sense maximum threshold vs duty cycle (programming slope compensation) oc (overcurrent) threshold vs temperature blank duration vs temperature blank duration vs r blank temperature (c) C50 5.0 comp sink current (ma) 12.5 0 50 75 42692 g19 10.0 7.5 C25 25 100 125 fb = 1.4vcomp = 1.6v temperature (c) C50 0 comp pin current (a) 5040 30 0 50 75 42692 g20 10 20 C25 25 100 125 fb = v ref comp = 1.6v comp (v) 0 0 i sense max threshold (mv) 240160 200120 1.0 2.0 2.5 42692 g21 40 80 0.5 1.5 3.0 t a = 25c r isense = 0k oc threshold temperature (c) C50 200 i sense max threshold (mv) 210 240 0 50 75 42692 g22 230 220 C25 25 100 125 comp = 2.5vr isense = 0k duty cycle (%) 0 0 i sense pin current (a) 10 40 20 50 60 42692 g23 30 20 10 30 40 80 70 90 100 t a = 25c duty cycle (%) 0 175 185 i sense max threshold (mv) 195 225 20 50 60 42692 g24 215 205 10 30 40 80 70 90 100 r slope = 1k r slope = 470 r slope = 0 t a = 25c comp = 2.5v temperature (c) C50 80 oc threshold (mv) 90 120 0 50 75 42692 g25 110 100 C25 25 100 125 precision overcurrent thresholdindependent of duty cycle temperature (c) C50 0 blank duration (ns) 200 800 0 50 75 42692 g26 600 400 C25 25 100 125 r blank = 40k r blank = 120k r blank (k) 0 0 blank (ns) 400200 1000 40 80 100 42692 g27 800 600 20 60 140 120 160 t a = 25c downloaded from: http:///
ltc4269-2 9 42692fb typical performance characteristics t delay : sout rise to out rise vs temperature t delay : sout rise to out rise vs r delay out rise/fall time vs out load capacitance out : max duty cycle vs f osc out : max duty cycle clamp vs sd_v sec out : max duty cycle clamp vs ss_maxdc ss_maxdc setting vs f osc (for out dc = 72%) ss_maxdc reset and active thresholds vs temperature temperature (c) C50 0 t delay (ns) 50 200 0 50 75 42692 g28 150 100 C25 25 100 125 r delay = 40k r delay = 120k r delay (k) 0 0 t delay (ns) 80 240 80 160 200 42692 g29 160 40 120 240 t a = 25c out load capacitance (pf) 0 0 out rise/fall time (ns) 5025 125 2000 3000 100 75 1000 4000 5000 t r t f 42692 g30 t a = 25c f osc (khz) 100 70 out duty cycle (%) 80 100 200 300 90 400 500 42692 g31 t a = 25c ss_maxdc = 2.5vsd_v sec = 1.4v sd_v sec (v) 1.32 0 70 out max duty cycle clamp (%) 80 90 1.65 1.98 6050 40 30 20 10 2.31 2.64 42692 g32 t a = 25c ss_maxdc = 1.84vf osc = 200khz r delay = 10k ss_maxdc (v) 1.60 20 70 out max duty cycle clamp (%) 80 90 1.84 2.08 6050 40 30 42692 g33 t a = 25c f osc = 200khz r delay = 10k sd_v sec = 1.32v sd_v sec = 1.98v sd_v sec = 2.64v f osc (khz) 100 1.60 2.08 ss_maxdc (v) 2.20 2.32 500 400 300 200 1.961.84 1.72 42692 g34 t a = 25c sd_v sec = 1.32v r delay = 10k 0 0.8 ss_maxdc (mv) 1.0 1.2 0.60.4 0.2 42692 g35 temperature (c) C50 0 50 75 C25 25 100 125 active threshold reset threshold downloaded from: http:///
ltc4269-2 10 42692fb pin functions shdn (pin 1): shutdown input. use this pin for auxiliary power application. drive shdn high to disable ltc4269-2 operation and corrupt the signature resistance. if unused, tie shdn to v portn . t2p (pin 2): type-2 pse indicator, open-drain. low impedance indicates the presence of a type-2 pse. r class (pin 3): class select input. connect a resistor between r class and v portn to set the classiication load current.v portn (pins 5, 6): power input. tie to the pd input through the diode bridge. pins 5 and 6 must be electrically tied together at the package. nc (pins 4, 7, 8, 25, 30, 31): no connect. comp (pin 9): output pin of the error ampliier. the error ampliier is an op amp, allowing various compensation networks to be connected between the comp pin and fb pin for optimum transient response in a nonisolated supply. the voltage on this pin corresponds to the peak current of the external fet. full operating voltage range is between 0.8v and 2.5v corresponding to 0mv to 220mv at the i sense pin. for applications using the 100mv oc pin for overcurrent detection, typical operating range for the comp pin is 0.8v to 1.6v. for isolated applications where comp is controlled by an opto-coupler, the comp pin output drive can be disabled with fb = v ref , reducing the comp pin current to (comp C 0.7)/40k. fb (pin 10): in a nonisolated supply, fb monitors the output voltage via an external resistor divider and is compared with an internal 1.23v reference by the error ampliier. fb connected to v ref disables error ampliier output. r osc (pin11): a resistor to gnd programs the operating frequency of the ic between 100khz and 500khz. nominal voltage on the r osc pin is 1.0v. sync (pin 12): used to synchronize the internal oscillator to an external signal. it is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. if unused, the pin should be connected to gnd. ss_maxdc (pin 13): the external resistor divider from v ref sets the maximum duty cycle clamp (ss_maxdc = 1.84v, sd_v sec = 1.32v gives 72% duty cycle). capacitor on ss_maxdc pin in combination with external resistor divider sets soft-start timing. v ref (pin 14): the output of an internal 2.5v reference which supplies internal control circuitry. capable of sourc- ing up to 2.5ma drive for external use. bypass to gnd with a 0.1f ceramic capacitor. sd_v sec (pin 15): the sd_v sec pin, when pulled below its accurate 1.32v threshold, is used to turn off the ic and reduce current drain from v in . the sd_v sec pin is con- nected to system input voltage through a resistor d ivider to deine undervoltage lockout (uvlo) for the power supply and to provide a volt-second clamp on the out pin. an 11a pin current hysteresis allows external programming of uvlo hysteresis. gnd (pin 16): analog ground. tie to v neg . blank (pin 17): a resistor to gnd adjusts the extended blanking period of the overcurrent and current sense ampliier outputs during fet turn-onto prevent false current limit trip. increasing the resistor value increases the blanking period. i sense (pin 18): the current sense input for the control loop. connect this pin to the sense resistor in the source of the external power mosfet. a resistor in series with the i sense pin programs slope compensation. downloaded from: http:///
ltc4269-2 11 42692fb oc (pin 19): oc is an accurate 107mv threshold, indepen- dent of duty cycle, for overcurrent detection and trigger of soft-start. connect this pin directly to the sense resistor in the source of the external power mosfet. delay (pin 20): a resistor to gnd adjusts the delay period between sout rising edge and out rising edge. used to maximize eficiency in forward converter applications by adjusting the timing. increasing the resistor value increases the delay period. pgnd (pin 21): power ground. carries the gate drivers return current. tie to v neg . out (pin 22): drives the gate of an n-channel mosfet between 0v and v in with a maximum limit of 13v on out pin set by an internal clamp. active pull-off exists in shutdown (see electrical speciication). v in (pin 23): input supply for the power supply controller. it must be closely decoupled to gnd. an internal under voltage lockout threshold exists for v in at approximately 14.25v on and 8.75v off. sout (pin 24): switched output in phase with out pin. provides sync signal for control of secondary-side fets in forward converter applications requiring highly eficient synchronous rectiication. sout is actively clamped to 12v. active pull-off exists in shutdown (see electrical speciication). can also be used to drive the active clamp fet of an active clamp forward supply. pin functions v neg (pins 26, 27): power output. connects the poe return line to the power supply through the internal hot swap power mosfet. pins 26 and 27 must be electrically tied together at the package. pwrgd (pin 28): active high power good output, open collector. signals that the internal hot swap mosfet is on. high impedance indicates power is good. pwrgd is referenced to v neg and is low impedance during inrush and in the event of thermal overload. pwrgd is clamped 14v above v neg . pwrgd (pin 29): active low power good output, open drain. signals that the internal hot swap mosfet is on. low impedance indicates power is good. pwrgd is referenced to v portn and is high impedance during inrush and in the event of thermal overload. pwrgd has no internal clamps.v portp (pin 32): input voltage positive rail. this pin is connected to the pds positive rail. exposed pad (pin 33): tie to gnd and pcb heat sink. downloaded from: http:///
ltc4269-2 12 42692fb block diagrams v ref >90% C + C + + C C + C + source2.5ma 2.5v 1.23v (100 to 500)khz osc (typical 200khz) i hyst 10a sd_v sec = 1.32v 0a sd_v sec > 1.32v 15 13 22 21 14 11 12 18 16 9 17 10 sd_v sec r osc sync 33 exposed pad 1.32v 1.23v adaptive maximum duty cycle clamp (linear) slope comp 8a 0% dc 35a 80% dc ramp s q r r q s blank fb comp gnd blank 20 delay v ref 23 v in ss_maxdc soft-start control over current sense current out 24 soutpgnd i sense 19 oc driver p 1a p 50ma 12v 13v 0.45v 42692 bd2 C + C + (voltage) error amplifier 107mv 0mv to 220mv on delay v in on v in off start-up input current (istart) C + bold line indicates high current path 32 t2p 2 r class 3 shdn pwrgd v portp 1 29 pwrgd 28 v neg 27 v neg 26 42692 bd1 control circuits classification current load ref C + 25k 16k v portn 6 v portn 5 en downloaded from: http:///
ltc4269-2 13 42692fb applications information overview power over ethernet (poe) continues to gain popularity as more products are taking advantage of having dc power and high speed data available from a single rj45 connector. as poe continues to grow in the marketplace, powered device (pd) equipment vendors are running into the 12.95w power limit established by the ieee 802.3af standard. the iee802.3at standard establishes a higher power allocation for power over ethernet while maintainin g backwards compatibility with the existing ieee 802.3af systems. power sourcing equipment (pse) and powered devices are distinguished as type 1 complying with the ieee 802.3af power levels, or type 2 complying with the ieee 802.3at power levels. the maximum available power of a type 2 pd is 25.5w. the ieee 802.3at standard also establishes a new method of acquiring power classiication from a pd and communi- cating the presence of a type 2 pse. a type 2 pse has the option of acquiring pd power classiication by performing 2-event classiication (layer 1) or by communicating with the pd over the data line (layer 2). in turn, a type 2 pd must be able to recognize both layers of communications and identify a type 2 pse. the ltc4269-2 is speciically designed to support a pd that must operate under the ieee 802.3at standard. in particular, the ltc4269-2 provides the t2p indicator bit which recognizes 2-event classiication. this indicator bit may be used to alert the ltc4269-2 output load that a type 2 pse is present. with an internal signature resis- tor, classiication circuitry, inrush control, and thermal shutdown, the ltc4269-2 is a complete pd interface solution capable of supporting in the next generation pd applications. in addition to the pd front end, the ltc4269-2 also incorporates a high eficiency synchronous forward controller that minimizes component sizes while maximiz- ing output power. modes of operation the ltc4269-2 has several modes of operation depend- ing on the input voltage applied between the v portp and v portn pins. figure 1 presents an illustration of voltage detection v1 classification on uvlo uvlo power bad uvlo on t = r load c1 pwrgd tracks v portn detection v2 50 time 4030 v portp (v) 2010 5040 30 20 10 time v portp C v neg (v) C10 time C20C30 v portp C pwrgd (v) pwrgd C v neg (v) C40C50 2010 pd current inrush dv dt inrush c1 = power bad pwrgd tracks v portp pwrgd tracks v portp power bad power bad timetime power good power good detection i 1 classification i class detection i 2 load, i load 42692 f01 i class dependent on r class selection inrush = 100ma i 1 = v1 C 2 diode drops 25k? i load = v portp r load i 2 = v2 C 2 diode drops 25k? v portp pse i in r load r class c1 r class pwrgd pwrgd ltc4269-2 v neg v portn in detectionrange figure 1. output voltage, pwrgd , pwrgd and pd current as a function of input voltage downloaded from: http:///
ltc4269-2 14 42692fb applications information and current waveforms the ltc4269-2 may encounter w ith the various modes of operation summarized in table 1. table 1. ltc4269-2 modes of operation as a function of input voltage v portp C v portn (v) ltc4269-2 modes of operation 0v to 1.4v inactive (reset after 1st classiication event) 1.5v to 9.8v (5.4v to 9.8v) 25k signature resistor detection before 1st classiication event (mark, 11k signature corrupt after 1st classiication event) 12.5v to on/uvlo classiication load current active on/uvlo to 60v inrush and power applied to pd load >71v overvoltage lockout, classiication and hot swap are disabled. on/uvlo includes hysteresis. rising input threshold: 37.2v max. falling input threshold: 30.0v min. these modes satisfy the requirements deined in the ieee 802.3af/at speciication. input diode bridge in the ieee 802.3af/at standard, the modes of operation reference the input voltage at the pds rj45 connector. since the pd must handle power received in either polarity from either the data or the spare pair, input diode bridges br1 and br2 are connected between the rj45 connector and the ltc4269-2 (figure 2). the input diode bridge introduces a voltage drop that af- fects the range for each mode of operation. the ltc4269-2 compensates for these voltage drops so that a pd built with the ltc4269-2 meets the ieee 802.3af/at-established voltage ranges. note that the electrical speciications are referenced with respect to the ltc4269-2 package pins. detection during detection, the pse looks for a 25k signature resis- tor which identiies the device as a pd. the pse will apply two voltages in the range of 2.8v to 10v and measures the corresponding currents. figure 1 shows the detection voltages v1 and v2 and the corresponding pd current. the pse calculates the signature resistance using the ? v/ ? i measurement technique. the ltc4269-2 presents its precision, temperature-com- pensated 25k resistor between the v portp and v portn pins, alerting the pse that a pd is present and requests power to be applied. the ltc4269-2 signature resistor also compensates for the additional series resistance introduced by the input diode bridge. thus a pd built with the ltc4269-2 conforms to the ieee 802.3af/at detection speciications. signature corrupt option in some designs that include an auxiliary power option, it is necessary to prevent a pd from being detected by a pse. the ltc4269-2 signature resistance can be corr upted with the shdn pin (figure 3). taking the shdn pin high will reduce the signature resistor below 11k which is an invalid signature per the ieee 802.3af/at speciicat ions, and alerts the pse not to apply power. invoking the shdn pin rx C 6 rx + 3 tx C 2 tx + rj45 t1 powered device (pd) input 42692 f02 1 78 5 4 spare C spare + to phy br2 0.1f100v br1 v portp d3 ltc4269-2 v portn figure 2. pd front end using diode bridge on main and spare inputs downloaded from: http:///
ltc4269-2 15 42692fb applications information also ceases operation for classiication and turns off the internal hot swap fet. if this feature is not used, connect shdn to v portn . classification classiication provides a method for more eficient power allocation by allowing the pse to identify a pd power clas- siication. class 0 is included in the ieee speciication for pds that dont support classiication. class 1-3 partitions pds into three distinct power ranges. class 4 includes the new power range under ieee 802.3at (see table 2). during classiication probing, the pse presents a ixed voltage between 15.5v and 20.5v to the pd (figure 1). the ltc4269-2 asserts a load current representing the pd power classiication. the classiication load current is programmed with a resistor r class that is chosen from table 2. table 2. summary of power classiications and ltc4269-2 r class resistor selection class usage maximum power levels at input of pd (w) nominal classification load current (ma) ltc4269-2 r class resistor (, 1%) 0 type 1 0.44 to 12.95 <0.4 open 1 type 1 0.44 to 3.84 10.5 124 2 type 1 3.84 to 6.49 18.5 69.8 3 type 1 6.49 to 12.95 28 45.3 4 type 2 12.95 to 25.5 40 30.9 2-event classification and the t2p pin a type 2 pse may declare the availability of high power by performing a 2-event classiication (layer 1) or by com- municating over the high speed data line (layer 2). a type 2 pd must recognize both layers of communication. since v portp v portn shdn ltc4269-2 signature disable 42692 f03 25k signatureresistor 14k to pse figure 3. 25k signature resistor with disable layer 2 communications takes place directly between the pse and the pd, the ltc4269-2 concerns itself only with recognizing 2-event classiication. in 2-event classiication, a type 2 pse probes for power classiication twice. figure 4 presents an example of a 2-event classiication. the 1st classiication event occurs detection v1 on uvlo uvlo uvlo on t = r load c1 tracks v portn detection v2 time pd current 5040 30 v portp (v) 2010 40ma 5040 30 20 10 time v portp C v neg (v) C10 time C20C30 v portp C t2p (v) C40C50 dv dt inrush c1 = 42692 f04 inrush = 100ma r class = 30.9? i load = v portp r load v portp pse i in r load r class c1 r class t2p ltc4269-2 v neg v portn 1st class 2nd mark detection i 1 detection i 2 2nd mark 2nd class 1st class 2nd class load, i load inrush 1st mark 1st mark figure 4. v neg , t2p and pd current as a result of 2-event classiication downloaded from: http:///
ltc4269-2 16 42692fb when the pse presents an input voltage between 15.5v to 20.5v and the ltc4269-2 presents a class 4 load cur- rent. the pse then drops the input voltage into the mark voltage range of 7v to 10v, signaling the 1st mark event. the pd in the mark voltage range presents a load current between 0.25ma to 4ma. the pse repeats this sequence, signaling the 2nd clas- siication and 2nd mark event occurrence. this alerts the ltc4269-2 that a type 2 pse is present. the type 2 pse then applies power to the pd and the ltc4269-2 charges up the reservoir capacitor c1 with a controlled inrush current. when c1 is fully charged, and the ltc4269-2 declares power good, the t2p pin presents an active low signal, or low impedance output with respect to v portn . the t2p output becomes inactive when the ltc4269-2 input voltage falls below the poe undervoltage lockout threshold. signature corrupt during mark as a member of the ieee 802.3at working group, linear noted that it is possible for a type 2 pd to receive a false indication of a 2-event classiication if a pse port is pre- charged to a voltage above the detection voltage range before the irst detection cycle. the ieee working group modiied the standard to prevent this possibility by requir- ing a type 2 pd to corrupt the signature resistance during the mark event, alerting the pse not to apply power. the ltc4269-2 conforms to this standard by internally cor- rupting the signature resistance. this also discharges the port before the pse begins the next detection cycle. pd stability during classification classiication presents a challenging stability problem due to the wide range of possible classiication load current. the onset of the classiication load current introduces a voltage drop across the cable and increases the forward voltage of the input diode bridge. this may cause the pd to oscillate between detection and classiication with the onset and removal of the classiication load current. the ltc4269-2 prevents this oscillation by introducing a voltage hysteresis window between the detection and clas- siication ranges. the hysteresis window accommodates the voltage changes a pd encounters at the onset of the classiication load current, thus providing a trouble-free transition between detection and classiication modes. the ltc4269-2 also maintains a positive i-v slope t hrough- out the classiication range up to the on voltage. in the event a pse overshoots beyond the classiication voltage range, the available load current aids in returning the pd back into the classiication voltage range. (the pd input may otherwise be trapped by a reverse-biased diode bridge and the voltage held by the 0.1f capacitor.) inrush current once the pse detects and optionally classiies the pd, the p s e then applies power to the pd. when the ltc4269-2 port voltage rises above the on voltage threshold, ltc4269-2 connects v neg to v portn through the internal power mosfet. to control the power-on surge currents in the system, the ltc4269-2 provides a ixed inrush current, allowing c1 to ramp up to the line voltage in a controlled manner. the ltc4269-2 keeps the pd inrush current below the pse current limit to provide a well-controlled power-up characteristic that is independent of the pse behavior. this ensures a pd using the ltc4269-2 interoperability with any pse. p oe undervoltage lockout the ieee 802.3af/at speciication for the pd dictates a maximum turn-on voltage of 42v and a minimum turn-off voltage of 30v. this speciication provides an adequate voltage to begin pd operation, and to discontinue pd op- eration when the port voltage is too low. in addition, this speciication allows pd designs to incorporate an on-off hysteresis window to prevent start-up oscillations. the ltc4269-2 features a poe undervoltage lockout (uvlo) hysteresis window (see figure 5) that conforms with the ieee 802.3af/at speciication and accommodates the voltage drop in the cable and input diode bridge at the onset of the inrush current. once c1 is fully charged, the ltc4269-2 turns on its inter- nal mosfet and passes power to the pd. the ltc4269-2 applications information downloaded from: http:///
ltc4269-2 17 42692fb continues to power the pd load as long as the port volt- age does not fall below the uvlo threshold. when the ltc4269-2 port voltage falls below the uvlo threshold, the pd is disconnected, and classiication mode resumes. c1 discharges through the ltc4269-2 circuitry. complementary power good when ltc4269-2 fully charges the load capacitor (c1), power good is declared and the ltc4269-2 load can safely begin operation. the ltc4269-2 provides complementary power good signals that remain active during normal operation and are deasserted when the port voltage falls below the poe uvlo threshold, when the voltage exceeds the overvoltage lockout (ovlo) threshold, or in the event of a thermal shutdown. see figure 6. the pwrgd pin features an open-collector output refer- enced to v neg which can interface directly with the sd_v sec pin. when power good is declared and active, the pwrgd pin is high impedance with respect to v neg . an internal 14v clamp limits the pwrgd pin voltage. connecting the pwrgd pin to the sd_v sec pin prevents the dc/dc converter from commencing operation before the pdi interface completely charges the reservoir capacitor, c1. the active low pwrgd pin connects to an internal, open- drain mosfet referenced to v portn and can interface directly to the shutdown pin of a dc/dc converter product. when power good is declared and active, the pwrgd pin is low impedance with respect to v portn . pwrgd pin when shdn is invoked in pd applications where an auxiliary power supply invokes the shdn feature, the pwrgd pin becomes high imped- ance. this prevents the pwrgd pin that is connected to the run pin of the dc/dc converter from interfering with the dc/dc converter operations when powered by an auxiliary power supply. overvoltage lockout the ltc4269-2 includes an overvoltage lockout (ovlo) feature (figure 5) which protects the ltc4269-2 and its load from an overvoltage event. if the input voltage ex- ceeds the ovlo threshold, the ltc4269-2 discontinues pd operation. normal operations resume when the input voltage falls below the ovlo threshold and when c1 is charged up. v portp c1 5f min v portn v neg ltc4269-2 42692 f05 to pse undervoltage overvoltage lockout circuit pd load current-limitedturn on + ltc4269-2 v portp C v portn power mosfet 0v to on* off >on* on ovlo off *includes on-uvlo hysteresis on threshold 36.1v uvlo threshold 30.7v ovlo threshold 71.0v figure 5. ltc4269-2 undervoltage and overvoltage lockout 42692 f06 bold line indicates high current path pwrgd power not good inrush complete on < v portp < ovlo and not in thermal shutdown v portp < uvlo v portp > ovlo or thermal shutdown power good 28 pwrgd ltc4269-2 29 v neg 27 v neg 26 v portn 6 v portn ovlo on uvlo tsd 5 control circuit figure 6. ltc4269-2 power good functional and state diagram applications information downloaded from: http:///
ltc4269-2 18 42692fb thermal protection the ieee 802.3af/at speci ication requires a pd to withstand any applied voltage from 0v to 57v indeinitely. however, there are several possible scenarios where a pd may encounter excessive heating. during classiication, excessive heating may occur if the pse exceeds the 75ms probing time limit. at turn-on , when the load capacitor begins to charge, the instantaneous power dissipated by the pd interface can be large before it reaches the line voltage. and if the pd experiences a fast input positive voltage step in its operational mode (for example, from 37v to 57v), the instantaneous power dissipated by the pd interface can be large. the ltc4269-2 includes a thermal protection feature which protects the ltc4269-2 from excessive heating. if the ltc4269-2 junction temperature exceeds the overtemp era- ture threshold, the ltc4269-2 discontinues pd opera tions. normal operation resumes when the junction temperature falls below the overtemperature threshold and when c1 is charged up and power good becomes inactive. external interface and component selection transformer nodes on an ethernet network commonly interface to the outside world via an isolation transformer. for pds, the isolation transformer must also include a center tap on the rj45 connector side (see figure 7). the increased current levels in a type 2 pd over a type 1 increase the current imbalance in the magnetics which can interfere with data transmission. in addition, proper termination is also required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. transformer vendors such as bel fuse, coilcraft, halo, pulse and tyco (table 4) can assist in selecting an appropriate isolation transformer and proper termination methods. table 4. power over ethernet transformer vendors vendor contact information bel fuse inc. 206 van vorst street jersey city, nj 07302 tel: 201-432-0463 www.belfuse.com coilcraft inc. 1102 silver lake road gary, il 60013 tel: 847-639-6400 www.coilcraft.com halo electronics 1861 landings drive mountain view, ca 94043 tel: 650-903-3800 www.haloelectronics.com pca electronics 16799 schoenborn street north hills, ca 91343 tel: 818-892-0761 www.pca.com pulse engineering 12220 world trade drive san diego, ca 92128 tel: 858-674-8100 www.pulseeng.com tyco electronics 308 constitution drive menlo park, ca 94025-1164 tel: 800-227-7040 www.circuitprotection.com input diode bridge figure 2 shows how two diode bridges are typically con- nected in a pd application. one bridge is dedicated to the data pair while the other bridge is dedicated to the spare pair. the ltc4269-2 supports the use of either silicon or schottky input diode bridges. however, there are tr ade-offs in the choice of diode bridges. an input diode bridge must be rated above the maximum current the pd application will encounter at the tempera- ture the pd will operate. diode bridge vendors typically call out the operating current at room temperature, but derate the maximum current with increasing temperature. consult the diode bridge vendors for the operating current de-rating curve. 1413 12 12 3 rx C 6 rx + 3 tx C 2 tx + rj45 t1 coilcraft eth1-230ld 42692 f07 17 8 5 4 10 9 11 56 4 d3 smaj58a tvs br1hd01 br2hd01 to phy v portp ltc4269-2 c1 v portn v neg spare C spare + c140.1f 100v figure 7. pd front end with isolation transformer, diode bridges, capacitors and a transient voltage suppressor (tvs) applications information downloaded from: http:///
ltc4269-2 19 42692fb a silicon diode bridge can consume over 4% of the a vailable power in some pd applications. using schottky diode s can help reduce the power loss with a lower forward voltage. a schottky bridge may not be suitable for some high temperature pd applications. the leakage current has a temperature and voltage dependency that can reduce the perceived signature resistance. in addition, the ieee 802.3af/at speci ication mandates the leakage back-feeding through the unused bridge cannot generate more than 2.8v across a 100k resistor when a pd is powered with 57v. sharing input diode bridges at higher temperatures, a pd design may be forced to consider larger bridges in a bigger package because the maximum operating current for the input diode bridge is drastically derated. the larger package may not be accept- able in some space-limited environments. one solution to consider is to reconnect the diode bridges so that only one of the four diodes conducts current in each package. this coniguration extends the maximum operating current while maintaining a smaller package proile. figure 7 shows how the reconnect the two diode bridges. consult the diode bridge vendors for the de-rating curve when only one of four diodes is in operation. input capacitor the ieee 802.3af/at standard includes an impedance requirement in order to implement the ac disconnect function. a 0.1f capacitor (c14 in figure 7) is used to meet this ac impedance requirement. place this capacitor as close to the ltc4269-2 as possible. transient voltage suppressor the ltc4269-2 speciies an absolute maximum voltage of 100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world can routinely see excessive peak voltages. to protect the ltc4269-2, install a transient voltage suppressor (d3) between the input diode bridge and the ltc4269-2 as close to the ltc4269-2 as possible as shown in figure 7. classiication resistor (r class ) the r class resistor sets the classiication load current, corresponding to the pd power classiication. select the value of r class from table 2 and connect the resistor between the r class and v portn pins as shown in figure 4, or loat the r class pin if the classiication load current is not required. the resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classiica- tion circuit. load capacitor the ieee 802.3af/at speciication requires that the pd maintains a minimum load capacitance of 5f and does not specify a maximum load capacitor. however, if the load capacitor is too large, there may be a problem with inadvertent power shutdown by the pse. this occurs when the pse voltage drops quickly. the input diode bridge reverses bias, and the pd load momentarily powers off the load capacitor. if the pd does not draw power within the pses 300ms disconnection delay, the pse may remove power from the pd. thus, it is necessary to evaluate the load current and capacitance to ensure that an inadvertent shutdown cannot occur. the load capacitor can store signiicant energy when fully charged. the pd design must ensure that this energy is not inadvertently dissipated in the ltc4269-2. for example, if the v portp pin shorts to v portn while the capacitor is charged, current will low through the parasitic body diode of the internal mosfet and may cause permanent damage to the ltc4269-2. t2p interface when a 2-event classiication sequence successfully completes, the ltc4269-2 recognizes this sequence, and provides an indicator bit, declaring the presence of a t ype 2 pse. the open-drain output provides the option to use this signal to communicate to the ltc4269-2 load, or to leave the pin unconnected. figure 8 shows two interface options using the t2p pin and the opto-isolator. the t2p pin is active low and connects to an optoisolater to communicate across the applications information downloaded from: http:///
ltc4269-2 20 42692fb these options come with various trade-offs and design considerations. contact linear technology applications support for detailed information on implementing custom auxiliary power sources. ieee 802.3 at system power-up requirement under the ieee 802.3at standard, a pd must operate under 12.95w in accordance with ieee 802.3at standard until it recognizes a type 2 pse. initializing pd operation in 12.95w mode eliminates interoperability issue in case a type 2 pd connects to a type 1 pse. once the pd rec- ognizes a type 2 pse, the ieee 802.3at standard requires the pd to wait 80ms in 12.95w operation before 25.5w operation can commence. maintain power signature in an ieee 802.3af/at system, the pse uses the maintain power signature (mps) to determine if a pd continues to require power. the mps requires the pd to periodica lly draw at least 10ma and also have an ac impedance less than 26.25k in parallel with 0.05f. if one of these conditions is not met, the pse may disconnect power to the pd. isolation the 802.3 standard requires ethernet ports to be el ectrically isolated from all other conductors that are user accessible. this includes the metal chassis, other connectors, and any auxiliary power connection. for pds, there are two com- mon methods to meet the isolation requirement. if there are any user-accessible connections to the pd, then an isolated dc/dc converter is necessary to meet the i solation requirements. if user connections can be avoided, then it is possible to meet the safety requirement by completely enclosing the pd in an insulated housing. switcher controller operation the ltc4269-2 has a current mode synchronous pwm controller optimized for control of a forward converter topology. the ltc4269-2 is ideal for power systems where very high eficiency and reliability, low complexity and cost are required in a small space. key features of the ltc4269-2 include an adaptive maximum duty cycle cl amp. figure 8. t2p interface examples applications information 42692 f08 option 1: series configuration for active low/low impedance output C54v to pse r p to pdsmicroprocessor to pds microprocessor v portp v portn t2p v + option 2: shunt configuration for active high/open collector output C54v to pse r p v portp ltc4269-2 ltc4269-2 v portn v neg t2p v + dc/dc converter isolation barrier. the pull-up resistor r p is sized according to the requirements of the opto-isola- tor operating current, the pull-down capability of the t2p pin, and the choice of v + . v + for example can come from the poe supply rail (which the ltc4269-2 v portp is tied to), or from the voltage source that supplies power to the dc/dc converter. option 1 has the advantage of not drawing power unless t2p is declared active. shutdown interface to corrupt the signature resistance, the shdn pin can be driven high with respect to v portn . if unused, connect shdn directly to v portn . exposed pad the ltc4269-2 uses a thermally enhanced dfn12 packa ge that includes an exposed pad. the exposed pad should be electrically connected to the gnd pins pcb copper plane. this plane should be large enough to serve as the heat sink for the ltc4269-2. auxiliary power source in some applications, it is desirable to power the pd from an auxiliary power source such as a wall adapter. auxiliary power can be injected into the pd at several locations with priority chosen between poe or auxiliary power sources. downloaded from: http:///
ltc4269-2 21 42692fb an additional output signal is included for synchronous recti ier control or active clamp control. a precision 10 7mv threshold senses overcurrent conditions and trigger s soft- start for low stress short-circuit protection and control. the key functions of the ltc4269-2 pwm controller are shown in the block diagrams. part start-up in normal operation, the sd_v sec pin must exceed 1.32v and the v in pin must exceed 14.25v to allow the part to turn on. this combination of pin voltages allows the 2.5v v ref pin to become active, supplying the ltc4269-2 control circuitry and providing up to 2.5ma external drive. sd_v sec threshold can be used for externally programming the power supply undervoltage lockout (uvlo) threshold on the input voltage to the forward converter. hysteresis on the uvlo threshold can also be programmed since the sd_v sec pin draws 11a just before part turn-on and 0a after part turn-on. with the ltc4269-2 turned on, the v in pin can drop as low as 8.75v before part shutdown occurs. this v in pin hysteresis (5.5v) combined with low 460a start-up input current allows low power start-up using a resistor/capaci- tor network from power supply input voltage to supply the v in pin (figure 10). the v in capacitor value is chosen to prevent v in falling below its turn-off threshold before a bias winding in the converter takes over supply to the v in pin. output drivers the ltc4269-2 has two outputs, sout and out. the out pin provides a 1a peak mosfet gate drive clamped to 13v. the sout pin has a 50ma peak drive clamped to 12v and provides sync signal timing for synchronous rectiication control or active clamp control. for sout and out turn-on, a pwm latch is set at the start of each main oscillator cycle. out turn-on is delayed from sout turn-on by a time, t delay (figure 14). t delay is programmed using a resistor from the delay pin to gnd and is used to set the timing control of the secondary synchronous rectiiers for optimum eficiency. sout and out turn off at the same time each cycle by one of three methods: (1) mosfet peak current sense at i sense pin (2) adaptive maximum duty cycle clamp reached during load/line transients (3) maximum duty cycle reset of the p wm latch during any of the following conditionslow v in , low sd_v sec or overcurrent detection at the oc pina soft- start event is latched and both sout and out turn off immediately (figure 11). leading edge blanking to prevent mosfet switching noise causing premature turn-off of sout or out, programmable leading edge blanking exists. this means both the current sense com- parator and overcurrent comparator outputs are ignored during mosfet turn-on and for an extended period after the out leading edge (figure 12). the extended blanking period is programmable by adjusting a resistor from the blank pin to gnd. adaptive maximum duty cycle clamp (volt-second clamp) for forward converter applications, a maximum switch duty cycle clamp which adapts to transformer input volt- age is necessary for reliable control of the mosfet. this volt-second clamp provides a safeguard for transformer reset that prevents transformer saturation. instantaneous load changes can cause the converter loop to demand maximum duty cycle. if the maximum duty cycle of the switch is too great, the transformer reset voltage can ex- ceed the voltage rating of the primary-side mosfets with catastrophic damage. many converters solve this problem by limiting the operational duty cycle of the mosfet to 50% or lessor by using a ixed (non-adaptive) maxim um duty cycle clamp with very large voltage rated mosfets. the ltc4269-2 provides a volt-second clamp to allow mosfet duty cycles well above 50%. this gives greater power utilization for the mosfets, rectiiers and trans- former resulting in less space for a given power output. in addition, the volt-second clamp can allow a reduced voltage rating on the mosfet resulting in lower r ds(on) for greater eficiency. the volt-second clamp deines a maximum duty cycle guard rail which falls when power supply input voltage increases. applications information downloaded from: http:///
ltc4269-2 22 42692fb an increase of voltage at the sd_v sec pin causes the maximum duty cycle clamp to decrease. if sd_v sec is resistively divided down from power supply input volt- age, a volt-second clamp is realized. to adjust the initial maximum duty cycle clamp, the ss_maxdc pin voltage is programmed by a resistor divider from the 2.5v v ref pin to gnd. an increase of programmed voltage on ss_maxdc pin provides an increase of switch maximum duty cycle clamp. soft-start the ltc4269-2 provides true pwm soft-start by using the ss_maxdc pin to control soft-start timing. the propor- tional relationship between ss_maxdc voltage and sw itch maximum duty cycle clamp allows the ss_maxdc pin to slowly ramp output voltage by ramping the maximum switch duty cycle clampuntil switch duty cycle clamp seamlessly meets the natural duty cycle of the converter. a soft-start event is triggered whenever v in is too low, sd_v sec is too low (power supply uvlo), or a 107mv overcurrent threshold at oc pin is exceeded. whenever a soft-start event is triggered, switching at sout and out is stopped immediately. the ss_maxdc pin is discharged and only released for charging when it has fallen below its reset threshold of 0.45v and all faults have been removed. increasing voltage on the ss_maxdc pin above 0.8v will increase switch maximum duty cycle. a capacitor to gnd on the ss_maxdc pin in combination with a resistor divider from v ref , deines the soft-start timing. current mode topology (i sense pin) the ltc4269-2 current mode topology eases frequency compensation requirements because the output induc- tor does not contribute to phase delay in the regulator loop. this current mode technique means that the error ampliier (nonisolated applications) or the opto-coupler (isolated applications) commands current (rather th an volt- age) to be delivered to the output. this makes frequency compensation easier and provides faster loop response to output load transients. a resistor divider from the applications output vo ltage gen- erates a voltage at the inverting fb input of the ltc4269-2 error ampliier (or to the input of an external opto-coupler) and is compared to an accurate reference (1.23v for ltc4269-2). the error ampliier output (comp) deines the input threshold (i sense ) of the current sense comparator. comp voltages between 0.8v (active threshold) and 2.5v deine a maximum i sense threshold from 0mv to 220mv. by connecting i sense to a sense resistor in series with the source of an external power mosfet, the mosfet peak current trip point (turn off) can be controlled by comp level and hence by the output voltage. an increase in output load current causing the output voltage to fall, will cause comp to rise, increasing i sense threshold, increasing the current delivered to the output. for isolated applications, the error ampliier comp output can be disabled to allow the opto-coupler to take control. setting fb = v ref disables the error ampliier comp output, reducing pin current to (comp C 0.7)/40k. slope compensation the current mode architecture requires slope compen sation to be added to the current sensing loop to prevent subhar- monic oscillations which can occur for duty cycles above 50%. unlike most current mode converters which have a slope compensation ramp that is ixed internally, placing a constraint on inductor value and operating frequency, the ltc4269-2 has externally adjustable slope compensation. slope compensation can be programmed by inserting an external resistor (r slope ) in series with the i sense pin. the ltc4269-2 has a linear slope compensation ramp which sources current out of the i sense pin of approximately 8a at 0% duty cycle to 35a at 80% duty cycle. overcurrent detection and soft-start (oc pin) an added feature to the ltc4269-2 is a precise 107mv sense threshold at the oc pin used to detect overcurrent conditions in the converter and set a soft-start latch. the oc pin is connected directly to the source of the primary- side mosfet to monitor peak current in the mosfet (fig- ure 13). the 107mv threshold is constant over the entire duty cycle range of the converter because it is unaffected by the slope compensation added to the i sense pin. applications information downloaded from: http:///
ltc4269-2 23 42692fb synchronizing a sync pin allows the ltc4269-2 oscillator to be synchro- nized to an external clock. the sync pin can be driven from a logic-level output, requiring less than 0.8v for a logic-level low and greater than 2.2v for a logic-level high. duty cycle should run between 10% and 90%. to avoid loss of slope compensation during synchronization, the free running oscillator frequency, f osc , should be programmed to 80% of the external clock frequency (f sync ). the r slope resistor chosen for nonsynchronized operation should be increased by 1.25x (= f sync /f osc ). shutdown and programming the power supply undervoltage lockout the ltc4269-2 has an accurate 1.32v shutdown thresh old at the sd_v sec pin. this threshold can be used in con- junction with a resistor divider to deine the power supply undervoltage lockout threshold (uvlo) of the power supply input voltage (v s ) (figure 9). a pin current hysteresis (11a before part turn-on, 0a after part turn-on) allows power supply uvlo hysteresis to be programmed. calculation of the on/off thresholds for the power supply input voltage can be made as follows: v s(off) threshold = 1.32[1 + (r1/r2)] v s(on) threshold = v s(off) + (11a r1) connect the pwrgd pin to the resistive divider network at the sd_v sec pin to prevent the dc/dc converter from starting before the pd interface completely charges the reservoir capacitor, c1 (figure 9). the sd_v sec pin must not be left open since there must be an external source current >11a to lift the pin past its 1.32v threshold for part turn-on. micropower start-up: selection of start-up resistor and capacitor for v in the ltc4269-2 uses turn-on voltage hysteresis at the v in pin and low start-up current to allow micropower start-up (figure 10). the ltc4269-2 monitors v in pin voltage to allow the part to turn-on at 14.25v and the part to turn- off at 8.75v. low start-up current (460a) allows a large resistor to be connected between the power supply input supply and v in . once the part is turned on, input current applications information figure 9. programming power supply undervoltage lockout (uvlo) 1.32v power supply input voltage (v s ) 42692 f09 sd_v sec pwrgd 11a ltc4269-2 r1r2 + C figure 10. low power start-up 1.32v power supply input voltage (v s ) from auxiliary winding *for v s > 25v, zener d1 recommended (v in on(max) < v z < 25v) 42692 f10 v in ltc4269-2 c start d1* r start + C increases to drive the ic (5.2ma) and the output drivers (i drive ). a large enough capacitor is chosen at the v in pin to prevent v in falling below its turn-off threshold before a bias winding in the converter takes over supply to v in . this technique allows a simple resistor/capacitor f or start-up which draws low power from the system supply to the converter. for system input voltages exceeding the absolute ma ximum rating of the ltc4269-2 v in pin, an external zener should be connected from the v in pin to gnd. this covers the condition where v in charges past v in(on) but the part does not turn on because sd_v sec < 1.32v. in this condition, v in will continue to charge towards system v in , possibly exceeding the rating for the v in pin. the zener voltage should obey v in(onmax) < v z < 25v. downloaded from: http:///
ltc4269-2 24 42692fb programming oscillator frequency the oscillator frequency (f osc ) of the ltc4269-2 is pro- grammed using an external resistor, r osc , connected between the r osc pin and gnd. figure 11 shows typical f osc vs r osc resistor values. the ltc4269-2 free-run- ning oscillator frequency is programmable in the range of 100khz to 500khz. stray capacitance and potential noise pickup on the r osc pin should be minimized by placing the r osc resistor as close as possible to the r osc pin and keeping the area of the r osc node as small as possible. the ground side of the r osc resistor should be returned directly to the (analog ground) gnd pin. r osc can be calculated by: r osc = 9.125k [(4100k/f osc ) C 1] programming leading edge blank time for pwm controllers driving external mosfets, noise can be generated at the source of the mosfet during gate rise time and some time thereafter. this noise can potentially exceed the oc and i sense pin thresholds of the ltc4269-2 to cause premature turn-off of sout and out pi ns in addition to false trigger of soft-start. the ltc4269-2 provides a programmable leading edge blanking of the oc and i sense comparator outputs to avoid false current sensing during mosfet switching. blanking is provided in two phases (figure 12): the irst phase automatically blanks during gate rise time. gate rise times can vary depending on mosfet type. for this r eason the ltc4269-2 performs true leading edge blanking by automatically blanking oc and i sense comparator outputs until out rises to within 0.5v of v in or reaches its clamp level of 13v. the second phase of blanking starts after the leading edge of out has been completed. this phase is programmable by the user with a resistor connected from the blank pin to gnd. typical durations for this portion of the blanking period are from 45ns at r blank = 10k to 540ns at r blank = 120k. blanking duration can be approximated as: blanking (extended) = [45(r blank /10k)]ns (see graph in the typical performance characteristics section). programming current limit (oc pin) the ltc4269-2 uses a precise 107mv sense threshold at the oc pin to detect overcurrent conditions in the converter and set a soft-start latch. it is independent of duty cycle because it is not affected by slope compensa- tion programmed at the i sense pin. the oc pin monitors the peak current in the primary mosfet by sensing the voltage across a sense resistor (r s ) in the source of the mosfet. the overcurrent limit for the converter can be programmed by: o v ercurrent limit = (107mv/r s )(n p /n s ) C (?)(i ripple ) applications information figure 11. oscillator frequency, f osc , vs r osc r osc (k) 50 frequency (khz) 400 42692 f11 100 150 250 200 300 350 500450 400 350 300 250 200 150 100 figure 12. leading edge blank timing r blank (min) = 10k 10k < r blank b 240k 100ns (automatic) leading edge blanking (programmable) extended blanking current sense delay outblanking 42692 f12 0 xns x + 45ns [x + 45(r blank /10k)]ns downloaded from: http:///
ltc4269-2 25 42692fb applications information where: r s = sense resistor in source of primary mosfet i ripple = i p-p ripple current in the output inductor l1 n s = number of transformer secondary turns n p = number of transformer primary turns programming slope compensation the ltc4269-2 uses a current mode architecture to p rovide fast response to load transients and to ease frequency compensation requirements. current mode switching regulators which operate with duty cycles above 50% and have continuous inductor current must add slope compensation to their current sensing loop to prevent subharmonic oscillations. (for more information on slope compensation, see application note 19.) the ltc4269-2 has programmable slope compensation to allow a wide range of inductor values, to reduce susceptibility to pcb generated noise and to optimize loop bandwidth. the ltc4269-2 programs slope compensation by inserting a resistor, r slope , in series with the i sense pin (figure 13). the ltc4269-2 generates a current at the i sense pin which is linear from 0% duty cycle to the maximum duty cycle of the out pin. a simple calculation of i sense r slope gives an added ramp to the voltage at the i sense pin for programmable slope compensation. (see both graphs i sense pin current vs duty cycle and i sense maximum threshold vs duty cycle in the typical performance characteristics section.) current slope = 35a dc v (isense) = v source + (i sense r slope ) i sense = 8a + 35dc a dc = duty cycle for sync operation i sense(sync) = 8a + (k 35dc)a k = f osc /f sync 42692 f13 i sense out ltc4269-2 oc r s r slope v source figure 13. programming slope compensation 42692 f14 delay ltc4269-2 r delay t delay soutout figure 14. programming sout and out delay: t delay programming synchronous rectiier timing: sout to out delay (t delay ) the ltc4269-2 has an additional output sout which pro- vides a 50ma peak drive clamped to 12v. in applications requiring synchronous rectiication for high eficiency, the ltc4269-2 sout provides a sync signal for second- ary side control of the synchronous rectiier mosfets (figure 14). timing delays through the converter can cause non-optimum control timing for the synchronous rectiier mosfets. the ltc4269-2 provides a program- mable delay (t delay , figure 14) between sout rising edge and out rising edge to optimize timing control for the synchronous rectiier mosfets to achieve maximum eficiency gains. a resistor r delay connected from the delay pin to gnd sets the value of t delay . typical values for t delay range from 10ns with r delay = 10k to 160ns with r delay = 160k (see graph in the typical performance characteristics section).programming maximum duty cycle clamp for forward converter applications, a maximum switch duty cycle clamp which adapts to transformer input volt- age is necessary for reliable control of the mosfets. this volt-second clamp provides a safeguard for transformer reset that prevents transformer saturation. the ltc 4269-2 sd_v sec and ss_maxdc pins provide a capacitor-less, programmable volt-second clamp solution using simple resistor ratios (figure 15). an increase of voltage at the sd_v sec pin causes the maximum duty cycle clamp to decrease. deriving sd_v sec from a resistor divider connected to system input voltage downloaded from: http:///
ltc4269-2 26 42692fb (3) the maximum duty cycle clamp calculated in (2) should be programmed to be 10% greater than the maximum operational duty cycle calculated in (1). simple adjustment of maximum duty cycle can be achieved by adjusting ss_maxdc. example calculation for (2): for r t = 35.7k, r b = 100k, v ref = 2.5v, r delay = 40k, f osc = 200khz and sd_v sec = 1.32v, this gives ss_maxdc(dc) = 1.84v, t delay = 40ns and k = 1 maximum duty cycle clamp = 1 0.522(1.84/1.32) C (40ns 200khz) = 0.728 C 0.008 = 0.72 (duty cycle clamp = 72%) note 1: to achieve the same maximum duty cycle clamp at 100khz as calculated for 200khz, the ss_maxdc voltage should be reprogrammed by, ss_maxdc(dc) (100khz) = ss_maxdc(dc) (200khz) k (200khz)/k (100khz) = 1.84 1.0/1.055 = 1.74v (k = 1.055 for 100khz) note 2 : to achieve the same maximum duty cycle clamp while synchronizing to an external clock at the sync pin, the ss_maxdc voltage should be reprogrammed as, ss_maxdc (dc) (fsync) = ss_maxdc (dc) (200khz) [(fosc/fsync) + 0.09(fosc/200khz)0.6] for ss_maxdc (dc) (200khz) = 1.84v for 72% duty cycle ss_maxdc (dc) (fsync = 250khz) for 72% duty cycle = 1.84 [(200khz/250khz) + 0.09(1)0.6] = 1.638v programming soft-start timing the ltc4269-2 has built-in soft-start capability to provide low stress controlled start-up from a list of fault condi- tions that can occur in the application (see figures 16 and 17). the ltc4269-2 provides true pwm soft-start by applications information creates the volt-second clamp. the maximum duty cycle clamp can be adjusted by programming voltage on the ss_maxdc pin using a resistor divider from v ref . an increase of voltage at the ss_maxdc pin causes the maximum duty cycle clamp to increase. to program the volt-second clamp, the following steps should be taken: (1) the maximum operational duty cycle of the converter should be calculated for the given application. (2) an initial value for the maximum duty cycle clamp should be calculated using the equation below with a irst pass guess for ss_maxdc. note: since maximum operational duty cycle occurs at minimum system input voltage (uvlo), the voltage at the sd_v sec pin = 1.32v. max duty cycle clamp (out pin) = k 0.522(ss_maxdc(dc)/sd_v sec ) C (t delay f osc ) where: ss_maxdc(dc) = v ref (r b /(r t + r b ) sd_v sec = 1.32v at minimum system input voltage t delay = programmed delay between sout and out k = 1.11 C 5.5eC7 (f osc ) power supply input voltage adaptive duty cycle clamp input max duty cycle clamp adjust input *minimum allowable r t is 10k to guarantee soft-start pull-off 42692 f15 sd_v sec ss_maxdcv ref ltc4269-2 r1 r2 r b r t * figure 15. programming maximum duty cycle clamp downloaded from: http:///
ltc4269-2 27 42692fb applications information 42692 f16 t delay : programmable synchronous delay faults triggering soft-startv in < 8.75v orsd_v sec < 1.32v (uvlo) oroc > 107mv (overcurrent) soft-start latch reset:v in > 14.25v (> 8.75v if latch set by oc)and sd_v sec > 1.32v andoc < 107mv and ss_maxdc < 0.45v soft-start latch set soutout ss_maxdc 0.8v (active threshold)0.45v (reset threshold) 0.2v using the ss_maxdc pin to control soft-start timing. the proportional relationship between ss_maxdc voltage and switch maximum duty cycle clamp allows the ss_maxdc pin to slowly ramp output voltage by ramping the ma ximum switch duty cycle clampuntil switch duty cycle clamp seamlessly meets the natural duty cycle of the converter. a capacitor c ss on the ss_maxdc pin and the resistor divider from v ref used to program maximum switch duty cycle clamp, determine soft-start timing (figure 18). a soft-start event is triggered for the following faults: (1) v in < 8.75v, or (2) sd_v sec < 1.32v (uvlo), or (3) oc > 107mv (overcurrent condition) when a soft-start event is triggered, switching at sout and out is stopped immediately. a soft-start latch is set and ss_maxdc pin is discharged. the ss_maxdc pin ca n only recharge when the soft-start latch has been reset. note: a soft-start event caused by (1) or (2) above, also causes v ref to be disabled and to fall to gnd. soft-start latch reset requires all of the following: (a) v in > 14.25v*, and (b) sd_v sec > 1.32v, and (c) oc < 107mv, and (d) ss_maxdc < 0.45v (ss_maxdc reset threshold) *v in > 8.75v is okay for latch reset if the latch was only set by overcurrent condition in (3) above. ss_maxdc discharge timing it can be seen in figure 17 that two types of discharge can occur for the ss_maxdc pin. in timing (a) the fault that caused the soft-start event has been removed be- fore ss_maxdc falls to 0.45v. this means the soft-start latch will be reset when ss_maxdc falls to 0.45v and ss_maxdc will begin charging. in timing (b), the fa ult that caused the soft-start event is not removed until some time after ss_maxdc has fallen past 0.45v. the ss_maxdc pin continues to discharge to 0.2v and remains low until all faults are removed. figure 16. timing diagram figure 17. soft-start timing figure 18. programming soft-start timing soft-start event triggered timing (a): soft start fault removed before ss_maxdc falls to 0.45v ss_maxdc 0.8v (active threshold)0.45v (reset threshold) 42692 f17 timing (b): soft-start fault removed after ss_maxdc falls past 0.45v ss_maxdc 0.8v (active threshold)0.45v (reset threshold) 0.2v ss_maxdc charging modelss_maxdc(dc) = v ref [r b /(r t + r b )] r charge = [r t r b /(r t + r b )] ss_maxdc(dc) 42692 f18 ss_maxdc r charge ss_maxdcv ref ltc4269-2 ltc4269-2 r b c ss r t c ss downloaded from: http:///
ltc4269-2 28 42692fb applications information the time for ss_maxdc to fall to a given voltage can be approximated as: ss_maxdc(t fall )= (c ss /i dis ) [ss_maxdc(dc) C v ss(min) ] where: i dis = net discharge current on c ss c ss = capacitor value at ss_maxdc pin ss_maxdc(dc) = programmed dc voltage v ss(min) = minimum ss_maxdc voltage before recharge i dis ? 8e C4 + (v ref C v ss(min) )[(1/2r b ) C (1/r t )] for faults arising from (1) and (2): v ref = 100mv. for a fault arising from (3): v ref = 2.5v. ss_maxdc(dc) = v ref [r b /(r t + r b )] v ss(min) = ss_maxdc reset threshold = 0.45v (if fault removed before t fall ) example for an overcurrent fault (oc > 100mv), v ref = 2.5v, r t = 35.7k, r b = 100k, c ss = 0.1f and assume v ss(min) = 0.45v, i dis ? 8e C4 + (2.5 C 0.45)[(? 100k) C (1/35.7k)] = 8e C4 + (2.05)(C0.23e C4 ) = 7.5e C4 ss_maxdc(dc) = 1.84v ss_maxdc(t fall ) = (1e C7 /7.5e C4 ) (1.84 C 0.45)=1.85e C4 s if the oc fault is not removed before 185s then ss _maxdc will continue to fall past 0.45v towards a new v ss(min) . the typical v ol for ss_maxdc at 150a is 0.2v. ss_maxdc charge timing when all faults are removed and the ss_maxdc pin has fallen to its reset threshold of 0.45v or lower, the ss_maxdc pin will be released and allowed to charge. ss_maxdc will rise until it settles at its programmed dc voltagesetting the maximum switch duty cycle clamp. the calculation of charging time for the ss_maxdc pin between any two voltage levels can be approximated as an rc charging waveform using the model shown in figure 16. the ability to predict ss_maxdc rise time between a ny two voltages allows prediction of several key timing periods: (1) no switching period (time from ss_maxdc(dc) to v ss(min) + time from v ss(min) to v ss(active) ) (2) converter output rise time (time from v ss(active ) to v ss(reg) ; v ss(reg) is the level of ss_maxdc where maximum duty cycle clamp equals the natural duty cycle of the switch) (3) t ime for maximum duty cycle clamp within x% of target value the time for ss_maxdc to charge to a given voltage v ss is found by re-arranging: v ss (t) = ss_maxdc(dc) (1 C e (Ct/rc) ) to give, t = rc (C1) ln(1 C v ss /ss_maxdc(dc)) where, v ss = ss_maxdc voltage at time t ss_maxdc(dc) = programmed dc voltage setting maximum duty cycle clamp = v ref (r b /(r t + r b ) r = r charge (figure 16) = r t r b /(r t + r b ) c = c ss (figure 16) example (1) no switching period the period of no switching for the converter, when a soft- start event has occurred, depends on how far ss_maxdc can fall before recharging occurs and how long a fault ex- ists. it will be assumed that a fault triggering soft-start is removed before ss_maxdc can reach its reset threshold (0.45v). no switching period = t discharge + t charge t discharge = discharge time from ss_maxdc(dc) to 0.45v t charge = charge time from 0.45v to v ss(active) t discharge was already calculated earlier as 185s. downloaded from: http:///
ltc4269-2 29 42692fb applications information t charge is calculated by assuming the following: v ref = 2.5v, r t = 35.7k, r b = 100k, c ss = 0.1f and v ss(min) = 0.45v. t charge = t(v ss = 0.8v) C t(v ss = 0.45v) step 1: ss_maxdc(dc) = 2.5[100k/(35.7k + 100k)] = 1.84vr charge = (35.7k 100k/135.7k) = 26.3k step 2: t(v ss = 0.45v) is calculated from: t = r charge c ss (C1) ln(1 C v ss /ss_maxdc(dc)) = 2.63e 4 1e C7 (C1) ln(1 C 0.45/1.84) = 2.63e C3 (C1) ln(0.755) = 7.3e C4 s step 3: t(v ss = 0.8v) is calculated from: t = r charge c ss (C1) ln(1 C v ss /ssCmaxdc(dc)) = 2.63e 4 1e C7 (C1) ln(1 C 0.8/1.84) = 2.63e C3 (C1) ln(0.565) = 1.5e C3 s from step 1 and step 2 t charge = (1.5 C 0.73)e C3 s = 7.7e C4 s the total time of no switching for the converter due to a soft-start event = t discharge + t charge = 1.85e C4 + 7.7e C4 = 9.55e C4 s example (2) converter output rise time the rise time for the converter output to reach regulation can be closely approximated as the time between the start of switching (ss_maxdc = v ss(active) ) and the time where converter duty cycle is in regulation (dc(reg)) and no longer controlled by ss_maxdc (ss_maxdc = v ss(reg) ). converter output rise time can be expressed as: output rise time = t(v ss(reg) ) C t(v ss(active) ) step 1: determine converter duty cycle dc(reg) for output in regulation. the natural duty cycle dc(reg) of the converter depends on several factors. for this example it is assumed that dc(reg) = 60% for power supply input voltage near the power supply uvlo. this gives sd_v sec = 1.32v. also assume that the maximum duty cycle clamp pro- grammed for this condition is 72% for ss_maxdc(dc) = 1.84v, f osc = 200khz and r delay = 40k. step 2: calculate v ss(reg) to calculate the level of ss_maxdc (v ss(reg) ) that no longer clamps the natural duty cycle of the converter, the equation for maximum duty cycle clamp must be used (see previous section programming maximum duty cycle clamp). the point where the maximum duty cycle clamp meets dc(reg) during soft-start is given by: dc(reg) = max duty cycle clamp 0.6 = k 0.522(ss_maxdc(dc)/sd_v sec ) C (t delay f osc ) for sd_v sec = 1.32v, f osc = 200khz and r delay = 40k this gives k = 1 and t delay = 40ns. rearranging the above equation to solve for ss_maxdc = v ss(reg) = [0.6 + (t delay f osc )(sd_v sec )]/(k 0.522) = [0.6 + (40ns 200khz)(1.32v)]/(1 0.522) = (0.608)(1.32)/0.522 = 1.537v step 3: calculate t(v ss(reg )) C t(v ss(active) ) recall the time for ss_maxdc to charge to a given volt- age v ss is given by: t = r charge c ss (C1) ln(1 C v ss /ss_maxdc(dc)) (figure 16 gives the model for ss_maxdc charging) for r t = 35.7k, r b = 100k, r charge = 26.3k for c ss = 0.1f, this gives t(v ss(active) ) = t(v ss(0.8v) ) = 2.63e 4 1e C7 (C1) ln(1 C 0.8/1.84) = 2.63e C3 (C1) ln(0.565) = 1.5e C3 s t(v ss(reg) ) = t(v ss(1.537v) ) = 26.3k 0.1f C1 ln(1 C 1.66/1.84) = 2.63e C3 (C1) ln(0.146) = 5e C3 s the rise time for the converter output: = t(v ss(reg) ) C t(v ss(active) ) = (5 C 1.5)e C3 s = 3.5e C3 s downloaded from: http:///
ltc4269-2 30 42692fb applications information example (3) time for maximum duty cycle clamp to reach within x% of target value a maximum duty cycle clamp of 72% was calculated previ- ously in the section programming maximum duty cycle clamp. the programmed value used for ss_maxdc(dc) was 1.84v. the time for ss_maxdc to charge from its minimum va lue v ss(min) to within x% of ss_maxdc(dc) is given by: t(ss_maxdc charge time within x% of target) = t[(1 C (x/100) ss_maxdc(dc)] C t(v ss(min) ) for x = 2 and v ss(min) = 0.45v, t(0.98 1.84) C t(0.45) = t(1.803) C t(0.45) from previous calculations, t(0.45) = 7.3e C4 s. using previous values for r t , r b and c ss , t(1.803) = 2.63e C4 1e C7 (C1) ln(1 C 1.803/1.84) = 2.63e C3 (C1) ln(0.02) = 1.03e C2 s hence the time for ss_maxdc to charge from its mini- mum reset threshold of 0.45v to within 2% of its target value is given by: t(1.803) C t(0.45) = 1.03e C2 C 7.3e C4 = 9.57e C3 s downloaded from: http:///
ltc4269-2 31 42692fb typical application + t2p v neg v portn shdn smaj58a r class v portp pgnd gnd blank delay 82k 30.9 24k 158k 332k 133 bas516 bas516 pa2431nl bas516 10k irf6217 fds8880 fds8880 5.1 158k 22.1k 33k 1.5k 50m 2k 5.1 1.2k v portp 5v tlv431a ps2801-1-l v cc 2.2nf 2kv 51k 20k t2pto microcontroller 11.3k 3.65k 2692 ta02 22k 0.22f 100pf 0.1f r osc v ref fb comp i sense oc ss_maxdc fds2582 sd_v sec v in pwrgd s out ltc4269-2 0.1f 18vpdz18b 10f16v v cc 33k 237k 107k 10k s1b b1100 s 8 plcs 2.2f100v + 10f100v 10h do1608c-103 1mh do1608c-105 6.8h pg0702.682 10.0k out 4.7nf 1nf 5.1 1nf 0.1f 100v 4.7nf 250v 10nf + 220f6.3v pslv0j227m(12)a 5v5a 36vpdz36b bss63lt1 v portp 48v auxiliary power 54v from data pair 54v from spare pair bc857bf ps2801-1-l bas21 poe-based self-driven synchronous forward power supply load (a) 0.5 efficiency (%) 80 85 90 5 42692 ta02b 7565 70 1.5 2 1 3 2.5 4 4.5 3.5 95 42v50v 57v eficiency vs load current downloaded from: http:///
ltc4269-2 32 42692fb package description dkd package 32-lead plastic dfn (7mm 4mm) (reference ltc dwg # 05-08-1734 rev a) note: 1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) bottom viewexposed pad r = 0.115 typ 0.20 p 0.05 1 16 17 32 6.00 ref 6.43 p 0.10 2.65 p 0.10 4.00 p 0.10 0.75 p 0.05 0.00 C 0.05 0.200 ref 7.00 p 0.10 (dkd32) qfn 0707 rev a 0.40 bsc recommended solder pad layout apply solder mask to areas that are not soldered 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer 6.43 p 0.05 2.65 p 0.05 0.70 p 0.05 0.40 bsc 6.00 ref 3.10 p 0.05 4.50 p 0.05 0.40 p 0.10 0.20 p 0.05 package outline r = 0.05 typ downloaded from: http:///
ltc4269-2 33 42692fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 04/10 connected pwrgd pin to sd_v sec pin in typical applications circuits. added text clarifying connecting pwrgd pin to sd_v sec pin in shutdown and programming the power supply undervoltage lockout section of applications information. 1, 23, 31 23 (revision history begins at rev b) downloaded from: http:///
ltc4269-2 34 42692fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ?? linear technology corporation 2009 lt 0409 rev b ? printed in usa related parts part number description comments lt ? 1952 single switch synchronous forward controller synchronous controller, programmable volt-sec clamp, low start current ltc3803 current mode flyback dc/dc controller in thinsot? 200khz constant frequency, adjustable slope compensation, optimized for high input voltage applications ltc3805 adjustable frequency current mode flyback controller slope comp overcurrent protect, internal/external clock ltc3825 isolate no-opto synchronous flyback controller with wide input supply range adjustable switching frequency, programmable undervoltage lockout, accurate regulation without t rim, synchronous for high eficiency. ltc4257-1 ieee 802.3af pd interface controller 100v 400ma internal switch, programmable classiication dual current limit ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only, ieee-compliant pd detection and classiication, autonomous operation or i 2 c control ltc4259a-1 quad ieee 802.3af power over ethernet controller ac or dc disconnect ieee-compliant pd detection and classiication, autonomous operation or i 2 c control ltc4263 single ieee 802.3af power over ethernet controller ac or dc disconnect ieee-compliant pd detection and classiication, autonomous operation ltc4263-1 high power single pse controller internal switch, autonomous operation, 30w ltc4265 ieee 802.3at pd interface controller 2-event classiication signaling, programmable classiication, auxiliary support ltc4266 quad ieee 802.3at pse controller type 1 and 2 compliant, 180mw/port at 720ma, advanced power management, 4-point pd detection ltc4267-1/ ltc4267-3 ieee 802.3af pd interface with integrated switching regulator 100v 400ma internal switch, programmable classiication, 200khz or 300khz constant frequency pwm, interface and switcher optimized for ieee-compliant pd system. ltc4268-1 35w high power pd interface with integrated switching regulator 750ma mosfet, programmable classiication, synchronous no-opto flyback controller, 50khz to 250khz ltc4269-1 ieee 802.3at pd interface integrated switching regulator 2-event classiication, programmable classiication, synchronous no-opto flyback controller, 50khz to 250khz downloaded from: http:///

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